Highly Reliable SuperFlash® Embedded Memory Scaling for Low Power SoC

The novel source side injection approach used by SuperFlashreg provides substantially lower power programming than the traditional drain side channel hot electron programming method. The poly-poly erase structure of SuperFlash provides SoC designs with 3 orders of magnitude faster erase speed without the over-erase circuitry overhead and long test time. The basic physics of program and erase methods sets the foundation for low power and high reliability margins for both endurance and data retention. Second generation SuperFlash with smaller memory cell size maintains this fundamental advantage for SoC scaling. Using self-aligned word lines and source lines avoids the alignment factor of scaling. As the Vdd of basic CMOS scaling shrinks to 1.8~1.0 V, the fundamental limitation of traditional stack gate requires a word line read pump that creates additional circuit overhead and complicates the design. The 3^rd generation SuperFlash with split-gate cell and erase-gate can continuously scale the read voltage in lockstep with the basic CMOS Vdd without adding a word line read pump. Endurance of one million cycles with 1.8 V word line read operation is confirmed with the 3rd generation SuperFlash^reg memory cell technology.