Metrology and reliability of sub-45 nm Cu/ULK interconnects using multiline test structures

Author

Guedj, C. ; Arnal, V. ; Jayet, C. ; Arnaud, L.

Author_Institution

MINATEC, Grenoble

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

3

Abstract

We used a multiline test device to evaluate the electrical linewidth, height, resistivity and reliability of sub-45 nm Cu/ULK interconnects. For 45 nm cu linewidth, an activation energy of 0.47 eV and current exponent n~2 are measured. A typical failure current of 36.6 MA/cm² at 170degC is obtained. Through electrical characterizations and finite element simulations, the interest of this polyvalent device for future VLSI interconnects is demonstrated.

Keywords

VLSI; finite element analysis; integrated circuit interconnections; integrated circuit measurement; integrated circuit reliability; integrated circuit testing; Cu-ULK interconnects reliability; VLSI interconnects; electrical characterization; electrical linewidth; electron volt energy 0.47 eV; finite element simulation; multiline test structures; polyvalent device; resistivity evaluation; temperature 170 C; Conductivity; Current measurement; Electric resistance; Electrical resistance measurement; Finite element methods; Geometry; Metrology; Performance evaluation; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378953

Filename

4239521