Quantitative Evaluation of Line Width Roughness-Effect on Mosfet Electrical Properties Using a Large Array Test Structure

Author

Shibuya, Akira ; Mori, Shigetaka ; Kusakabe, Takanori ; Hiramatsu, Yoshihisa ; Matsuzawa, Nobuyuki ; Ando, Atsuhiro ; Kanno, Michihiro ; Nagashima, Naoki

Author_Institution

Sony Corp. Atsugi Tec., Atsugi

fYear

2007

fDate

23-25 April 2007

Firstpage

1

Lastpage

2

Abstract

Variation of the device performances of MOSFET (gate length (L_gate) of 60 nm) due to random line width roughness (LWR) were evaluated through random variation after extracting smoothly changing "systematic" part fitted on the 4th-order polynomial function using a large array test structure. Our results directly suggest that 3sigma_LWR/L_gate-decrease of 0.9% causes 0.046 of decrease in leakage current variation (3sigma(log(I_off))). Reduction of the variation causes better device performance (1.8% up in drive current (I_on) performance).

Keywords

MOSFET; leakage currents; polynomials; semiconductor device testing; MOSFET electrical properties; device performance variation; fourth-order polynomial function; large array test structure; leakage current variation; line width roughness-effect; quantitative evaluation; size 60 nm; Data mining; Fluctuations; Gaussian distribution; Leakage current; MOS devices; MOSFET circuits; Performance evaluation; Polynomials; Semiconductor device measurement; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on

Conference_Location

Hsinchu

ISSN

1524-766X

Print_ISBN

1-4244-0584-X

Electronic_ISBN

1524-766X

Type

conf

DOI

10.1109/VTSA.2007.378956

Filename

4239524