TMS320C30 DSP based implementation of a half rate CELP coder

A real-time, TMS320C30 digital signal processor (DSP)-based implementation of a 4.3-kbit/s speech coder targeted for the E-TDMA half-rate digital cellular system is presented. The speech coding algorithm is based on code excited linear prediction (CELP) technology. It features a 25-bit line spectral frequency split vector quantizer for encoding the short-term parameters, a 7-bit adaptive codebook, and a 9-bit fixed stochastic codebook. The short-term parameters, i.e., the line spectral frequency vector quantization indices, are updated every 20 ms and the excitation parameters i.e., the adaptive and fixed codebook indices and their gains, are updated every 8 ms. An overview is provided of the speech coding algorithm, the hardware platform architecture, the firmware development methodology, techniques used for optimizing the firmware of the real-time critical section of the algorithm, and speech quality monitoring methods employed during the firmware development