Title :
Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies
Author :
Schruefer, K. ; von Arnim, K. ; Pacha, C. ; Berthold, J. ; Cleavelin, C.R. ; Schulz, T. ; Xiong, W. ; Patruno, P.
Author_Institution :
Infineon Technol., Munich
Abstract :
A multi-gate CMOS technology for low-power applications with highly competitive digital performance is presented. Ring oscillators with metal gates and undoped fins are measured with high yield demonstrating the capability of large scale integration. An inverter delay of 15 ps and 0.5 nA/stage off-current at Vdd=1.2 V shows an improved leakage-performance trade-off compared to 65 nm low-standby power CMOS technologies. Scalability to 32 nm and beyond is shown.
Keywords :
CMOS digital integrated circuits; field effect transistor circuits; large scale integration; leakage currents; low-power electronics; oscillators; inverter delay; large scale integration; leakage performance; low-power multigate CMOS technologies; metal gates; multigate FET; ring oscillators; undoped fins; CMOS process; CMOS technology; Circuit optimization; Delay; Digital circuits; Frequency; Instruments; Leakage current; Stress; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0584-X
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2007.378961
