FPGA Implementation of Hybrid Additive Programmable Cellular Automata Encryption Algorithm

This paper presents a hardware implementation in a FPGA circuit of an efficient encryption algorithm based on hybrid additive programmable cellular automata (HAPCA). We present a novel approach for a high-speed encryption system prototyped using a single FPGA. The approach is based upon a one-dimensional HAPCA architecture. A regular, modular, and cascadable hardware implementation of the cellular automata encryption algorithm has been implemented, which is efficient in terms of VLSI technology. The encryption algorithm based on the theory of cellular automata was realized using simple digital circuits and memory, and we implemented it on an emulation platform based on FPGA circuit. The experimental results prove the powerful of cellular automata encryption systems. The design has been specified in VHDL targeted on a XILINX XC3S400 based FPGA and verified for functional correctness by software simulation.