Title :
35nm SOI-CMOS for Sub-Ambient Temperature Operation
Author :
Cai, Jin ; Frank, David J. ; Yin, Haizhou ; Dennard, Robert H. ; Haensch, Wilfried E.
Author_Institution :
IBM, Yorktown Heights
Abstract :
We demonstrate over 40% CMOS performance gain with minimal process changes by lowering the operating temperature from 100degC to -50degC. For the same performance, the lower temperature operation delivers a 60% reduction in power-delay product at a reduced supply voltage. Coupled with recent advances in liquid cooling techniques, our results suggest that sub-ambient temperature operation is an attractive option for high performance and energy-efficient CMOS.
Keywords :
MOSFET; semiconductor device testing; silicon-on-insulator; NFET; PFET; SOI-CMOS; liquid cooling techniques; power-delay product; sub-ambient temperature operation; voltage scaling barrier; CMOS technology; Coolants; Electric resistance; Energy efficiency; Immune system; Performance gain; Stress; System performance; Temperature; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
1-4244-0584-X
Electronic_ISBN :
1524-766X
DOI :
10.1109/VTSA.2007.378969
