• DocumentCode
    2849840
  • Title

    Low Threshold Voltage CMOSFETs with NiSi Fully Silicided Gate and Modified Schottky Barrier Source/Drain Junction

  • Author

    Lin, Chia-Pin ; Tsui, Bing-Yue ; Hsieh, Chih-Ming ; Huang, Chih-Feng

  • Author_Institution
    Nat. Chiao Tung Univ., Hsinchu
  • fYear
    2007
  • fDate
    23-25 April 2007
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Low threshold voltage CMOSFETs with NiSi fully silicided gate and Modified Schottky barrier source/drain junction were fabricated. Symmetric threshold voltage was obtained by implant-to-silicide technique. Lateral growth rate and thermal stability of NiSi on SiO2 were investigated. Single silicide and low temperature process make the proposed process very promising in sub - 45 nm technology nodes.
  • Keywords
    CMOS integrated circuits; MOSFET; Schottky barriers; semiconductor junctions; CMOSFET; Schottky barrier source/drain junction; silicide technique; symmetric threshold voltage; Annealing; CMOSFETs; Doping; Schottky barriers; Silicides; Substrates; Temperature; Thermal resistance; Thermal stability; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
  • Conference_Location
    Hsinchu
  • ISSN
    1524-766X
  • Print_ISBN
    1-4244-0584-X
  • Electronic_ISBN
    1524-766X
  • Type

    conf

  • DOI
    10.1109/VTSA.2007.378970
  • Filename
    4239538
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2849840