A CMOS bandgap reference with high PSRR and improved temperature stability for system-on-chip applications

Author

Dey, Abhisek ; Bhattacharyya, Tarun Kanti

Author_Institution

Dept. of E & ECE, Indian Inst. of Technol., Kharagpur, India

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

A high precision temperature compensated CMOS bandgap reference is implemented in UMC 0.18μm RF/CMOS process. The proposed circuit employs current-mode architecture that removes the supply as well as reference voltage limitations. Using only first order compensation the new architecture can generate an output reference voltage of 600mV with a variation of 400μV over a wide temperature range from +20°C to +100°C which corresponds to a temperature coefficient of 5.5ppm/°C. The output reference voltage exhibits a variation of 2mV for supply voltage ranging from 1.6V to 2.0V. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The presented bandgap reference occupies only 0.09 mm² layout area.

Keywords

CMOS integrated circuits; system-on-chip; thermal stability; RF-CMOS process; UMC; current-mode architecture; first order compensation; high PSRR; high precision temperature compensated CMOS bandgap reference; improved temperature stability; reference voltage limitations; size 0.18 mum; system-on-chip applications; temperature -20 degC to 100 degC; voltage 1.6 V to 2.0 V; voltage 2 mV; voltage 400 muV; voltage 600 mV; CMOS integrated circuits; Photonic band gap; Power supplies; Resistors; System-on-a-chip; Temperature distribution; Voltage control; BGR; Current-mode; PSRR; Temperature coefficient;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117640

Filename

6117640