A delta-sigma fractional-N frequency divider for a Phase Lock Loop in 60GHz transceiver

Author

Wang, Yisheng ; Ma, Kaixue ; Mahalingam, Nagarajan ; Yeo, Kiat Seng

Author_Institution

Nanyang Technol. Univ., Singapore, Singapore

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

A design and optimization flow for digital delta-sigma fractional-N frequency divider of Phase Lock Loop (PLL) is introduced in this paper. The low power design is used for the 60 GHz RF transceiver using 0.18μm SiGe BiCMOS technology. With full consideration of the low complexity and unconditional stability, MASH111 delta-sigma modulator is chosen as control module for the PLL. The input frequency is 6.48Ghz, and the integer division rate is from 36 to 64 with step of 2.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; delta-sigma modulation; field effect MIMIC; frequency dividers; millimetre wave frequency convertors; phase locked loops; radio transceivers; BiCMOS technology; MASH delta-sigma modulator; SiGe; delta-sigma fractional-N frequency divider; frequency 6.48 GHz; frequency 60 GHz; integer division rate; low power design; multistage noise shaping; optimization flow; phase lock loop; size 0.18 mum; transceivers; Frequency conversion; Frequency modulation; Frequency synthesizers; Noise; Optimization; Phase locked loops; 60GHz RF transceiver; Delta-Sigma modulator; MASH111; SiGe BiCOMS; fractional-N PLL; frequency synthesizer;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117645

Filename

6117645