Platform-based synthesis design methodology for system-on-chips

Platform-based design for system-on-chips (SoCs) uses existing designs as starting points for new system implementations and put more stress on system level reuse. Synthesis methods are important elements in platform-based design methodologies. This paper takes hardware/software (HW/SW) co-design and high level design reuse as keys to SoC design. First, it introduces a system level co-exploration methodology and presents a typical platform-based design flow. Then it emphasizes performance analysis; considering a problem called the first-generation dilemma, proposes a revised platform-based design flow. To support design technology innovations, several synthesis issues are discussed, such as platform reuse, configurable architecture, and system level verification. In addition, it adopts market-oriented views and synthesis tools such as Cadence VCC to make the design practical.