• DocumentCode
    2850145
  • Title

    COS/MOS parallel processor array

  • Author

    Alaspa, A. ; Dingwall, A.

  • Author_Institution
    RCA Aerospace Systems Division, Burlington, MA, USA
  • Volume
    XIII
  • fYear
    1970
  • fDate
    18-20 Feb. 1970
  • Firstpage
    118
  • Lastpage
    119
  • Abstract
    A report on an LSI, COS/MOS parallel processor array posessing functional capabilities of an arithmetic unit 4-bit slice, will be presented. High functional density was achieved using functional gating and transmission gating to reduce device requirements. The data-transfer rate for a 4-bit add is 1.4 μs including instruction decode.
  • Keywords
    Arithmetic; Concurrent computing; Decoding; Flip-flops; Large scale integration; Logic arrays; Logic devices; NASA; Programmable logic arrays; Shift registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1970 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1970.1154867
  • Filename
    1154867
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2850145