• DocumentCode
    2850326
  • Title

    Dynamic Verifying The Properties of The Simple Subset of PSL

  • Author

    Jin, Naiyong ; Shen, Chengjie

  • Author_Institution
    East China Normal Univ., Shanghai
  • fYear
    2007
  • fDate
    6-8 June 2007
  • Firstpage
    229
  • Lastpage
    240
  • Abstract
    PSL is a standard specification language(IEEE-1850) for hardware and embedded system design. The simple subset of PSL(PSLSimple) conforms to the notion of monotonic advancement of time, which in turn ensures that formulas within the subset can be simulated easily. Dynamic verifiers consider only finite executions which may be too short to assure their satisfaction to some formulas. In this paper, we work on the theories and methods for designing dynamic verifiers for PSLSimple. We first study the formalism for the formula satisfaction strengths over finite words. Then, we explore the combinational laws of finite words with respect to strong satisfaction, weak satisfaction and strong violation. That contributes acceptance conditions for automata to recognize not just violating, but also strongly satisfying and pending words for all PSLsimple structures. In the end, we propose the local-variable-enhanced alternating finite automata( LAFA) as the run time checkers for PSLSimple. The size of a LAFA is linear to the size of its PSLSimple formula.
  • Keywords
    embedded systems; finite automata; specification languages; dynamic verifier; embedded system design; finite automata; property specification language; Automata; Design engineering; Design methodology; Embedded system; Formal specifications; Hardware; Logic; Specification languages; Testing; Time to market;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Theoretical Aspects of Software Engineering, 2007. TASE '07. First Joint IEEE/IFIP Symposium on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-0-7695-2856-4
  • Type

    conf

  • DOI
    10.1109/TASE.2007.20
  • Filename
    4239967