A 65nm CMOS low power delay line based temperature sensor

Author

Xie, Shuang ; Ng, Wai Tung

Author_Institution

Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

fYear

2011

fDate

17-18 Nov. 2011

Firstpage

1

Lastpage

2

Abstract

In this paper, a fully digital delay line based temperature sensor is presented for on-chip thermal monitoring. Unlike previous delay line temperature sensors, the proposed design employs a 2^N to N tab decoding along with counter and in this way dynamic power is saved by a factor of 2^N. Post-layout simulation for a 65nm CMOS design shows that the proposed sensor consumes 0.02 nJ energy per conversion and it has a resolution of 1.0 °C with errors less than ±3.0 °C over a temperature range from 0 to 100 °C.

Keywords

CMOS integrated circuits; delay lines; low-power electronics; temperature sensors; CMOS low power delay line; digital delay line; energy 0.02 nJ; on-chip thermal monitoring; size 65 nm; tab decoding; temperature 0 degC to 100 degC; temperature sensor; CMOS integrated circuits; Decoding; Delay lines; Energy resolution; Radiation detectors; Ring oscillators; Temperature sensors; delay line temperature sensor; low power; power management; ring oscillator; thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of

Conference_Location

Tianjin

ISSN

Pending

Print_ISBN

978-1-4577-1998-1

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/EDSSC.2011.6117665

Filename

6117665