Power gating technique in pacemaker design on FPGA

This study presents power gating techniques to reduce the power consumption in pacemaker device. A novel structure based on power technique in pacemaker device is presented. Experimental results in power reduction and cost overhead by using proposed structure are given. The result in saving power consumption-up to 25%- would be promising because the structure could last usage time of pacemaker device longer than normal structure. However, the cost overhead appears but is smaller than 0.65% in indicators of logic element, combinational function, and logic register.