Abstract :
The following topics are dealt with: memory test, online testing & test generation; mixed signal and RF design; FPGA-based design; BIST; fault tolerance and analysis; DFT and low power design; fault modeling & analysis; design verification & optimization; analog and mixed-signa test; SOC/NOC/MPSOC; and layout design & verification.
Keywords :
automatic test pattern generation; built-in self test; design for testability; fault tolerance; field programmable gate arrays; formal verification; integrated circuit layout; logic design; network-on-chip; BIST; DFT; FPGA-based design; MPSOC; NOC; RF design; analog testing; fault analysis; fault modeling; fault tolerance; layout design; low power design; memory testing; mixed signal design; mixed-signal testing; online testing; optimization; test generation; verification;
Conference_Titel :
Design and Test Workshop, 2007. IDT 2007. 2nd International
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-1824-4
DOI :
10.1109/IDT.2007.4437404
