A methodology for selection of analog hardware for back-propagation algorithm implementation

A methodology is presented for the selection of analog hardware components for the VLSI implementation of the backpropagation learning algorithm. The methodology makes use of a combination of theoretical analysis of error due to analog hardware non-idealities, as well as a procedure for modeling of the behaviour of these non-idealities. The theoretical analysis provides upper bounds on the errors for successful learning as well as for successful recognition of unknown patterns after learning has been completed. The modeling procedure helps to translate the errors due to hardware non-idealities to a form suitable for the theoretical analysis procedure. The bounds derived from the theoretical analysis are verified by simulating the backpropagation algorithm for a sample application, with the errors contained in it. The theoretical bounds are found to agree with the simulation results