An implementable digital multilayer neural network (DMNN)

Modular implementation of digital multilayer neural networks (DMNNs) is discussed. The use of simple logic gates for neural operations and the modular design techniques lead to a compact, expandable architecture of the DMNN suitable for VLSI implementation. A DMNN architecture for recognizing characters is presented and its performance is evaluated. The architecture and all digital sub-components in the DMNN are modeled and simulated in VHDL (VHSIC Hardware Description Language). The modular design technique is extremely efficient, especially in building multilayered neural networks, since they can be simply constructed by connecting any desired number of modules. Full parallelism is utilized in the DMNN architecture. Its processing speed depends only on the clock frequency and register lengths, not on the network size. About 200000 patterns per second are classified for a 9-bit register length and 50-MHz clock. The classification performance of the DMNN five-digit recognizer is shown to be competitive in terms of classification rates when the register length is greater than eight