DocumentCode
285117
Title
The use of cache memory in neurocomputer design
Author
Tay, O.N. ; Noakes, P.D.
Author_Institution
Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK
Volume
2
fYear
1992
fDate
7-11 Jun 1992
Firstpage
571
Abstract
The authors present the results of a study of the suitability and performance of cache memory when used in neural network computing. Two methods of allocating interconnection weights to a cache memory are presented and compared. The results for these two methods have been obtained by using 16 neural network examples as the simulation workloads. It is shown that cache memory can be efficiently used in neural network computing if an appropriate allocation of interconnection weights is chosen. The use of partitioning is suitable for a multiprocessor system. This is because each partition within the same layer is independent and allows the mapping of these partitions in a neural network onto a multiprocessor system with reduced communication bandwidth. The only parameter that needs to be passed between processors is the state values. It is shown that by partitioning the network before allocating the weights to cache memory, the weight table cache performance is minimally affected by the number of interconnection weights required by a neural network
Keywords
buffer storage; neural nets; storage management; virtual machines; cache memory; interconnection weight allocation; interconnection weights; multiprocessor; neural network computing; neurocomputer design; partitioning; simulation workloads; state values; suitability; weight table cache performance; Bandwidth; Cache memory; Computational modeling; Computer architecture; Computer networks; Computer vision; Neural networks; Neurons; Random access memory; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1992. IJCNN., International Joint Conference on
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-0559-0
Type
conf
DOI
10.1109/IJCNN.1992.226927
Filename
226927
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