A new approach and tool in verifying asynchronous circuits

EDA tools have been considered long time ago in hardware design. Some tools have also been proposed for asynchronous circuits, an emerged approach to overcome the clock distribution problem, the main drawback of synchronous circuits. However, they are lack of methods for verifying the correctness of the produced circuits. This work is about a new version of the PAiD tool developed at HCMC University of Technology that can enable engineers to design, verify and synthesize asynchronous circuits. Experiments in verifying circuits have been also provided in this work.