DocumentCode
2851216
Title
New upper bound of target array for reconfigurable VLSI arrays
Author
Jigang, Wu ; Han, Xiaogang
Author_Institution
Sch. of Comput. Sci. & Software, Tianjin Polytech. Univ., Tianjin, China
fYear
2011
fDate
17-18 Nov. 2011
Firstpage
1
Lastpage
2
Abstract
Reconfiguring a VLSI array with faults is to construct a maximum logical sub-array (target array). A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for the VLSI arrays with clustered faults. Simulation results show that the upper bound is reduced up to 20% on 256 × 256 array with clustered faults.
Keywords
VLSI; fault diagnosis; integrated circuit design; logic arrays; logic design; reconfigurable architectures; clustered fault; maximum logical subarray; reconfigurable VLSI arrays; reconfiguration algorithm; target array; upper bound; Arrays; Clustering algorithms; Computers; Fault tolerance; Switches; Upper bound; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2011 International Conference of
Conference_Location
Tianjin
ISSN
Pending
Print_ISBN
978-1-4577-1998-1
Electronic_ISBN
Pending
Type
conf
DOI
10.1109/EDSSC.2011.6117702
Filename
6117702
Link To Document