DocumentCode
2851269
Title
Using Reconfigurable Computers for DSP Image Processing
Author
Taher, Mohamed ; El-Ghazawi, Tarek
Author_Institution
Ain Shams Univ., Cairo
fYear
2007
fDate
16-18 Dec. 2007
Firstpage
55
Lastpage
60
Abstract
Reconfigurable computers (RCs) are those parallel systems that are designed around multiple general-purpose processors and multiple field programmable gate array (FPGA) chips. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. RCs have proposed very high processing capabilities for computationally intensive applications such as Image Processing. This is due to the inherently parallel operation paradigm of the FPGA hardware. In this paper we present the design and implementation of image processing kernels for RCs. This library of kernels have been tested and verified for performance on one of the state-of-the-art reconfigurable computers, SRC-6E. This paper shows that RCs are between 8 to 400 times faster than comparable Pentiums for image based tasks.
Keywords
field programmable gate arrays; image processing; reconfigurable architectures; DSP image processing; SRC-6E; low-level hardware functionality; multiple field programmable gate array chips; multiple general-purpose processors; parallel systems; reconfigurable computers; Application software; Computer applications; Concurrent computing; Digital signal processing; Digital signal processing chips; Field programmable gate arrays; Hardware; Image processing; Kernel; Libraries;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Workshop, 2007. IDT 2007. 2nd International
Conference_Location
Cairo
Print_ISBN
978-1-4244-1824-4
Electronic_ISBN
978-1-4244-1825-1
Type
conf
DOI
10.1109/IDT.2007.4437428
Filename
4437428
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