Measurement Environment for Reliability Study of High Current First Level Interconnections

Author

Barton, Zdenek ; Horky, Jiri ; Duda, Radoslav ; Szendiuch, Ivan ; Novotny, Marek ; Gevaert, Dorine

Author_Institution

CEDO Ltd., Brno

fYear

2007

fDate

16-18 Dec. 2007

Firstpage

66

Lastpage

67

Abstract

Reliability of integrated circuits in electronic packages and connections is a major concern, due to the increasing die size, power dissipation and temperature. The extension of existing interconnection technologies towards higher current/power handling capabilities is a challenging and demanding task. In this paper a powerful system for experimental evaluation and reliability study for high current first level interconnections, up to 20 A, is presented. The system is used for evaluation of wire and flip-chip interconnections.

Keywords

flip-chip devices; integrated circuit reliability; flip-chip interconnections; high current first level interconnections; integrated circuits reliability; measurement environment; power dissipation; reliability study; wire evaluation; Current measurement; Electronics packaging; Integrated circuit interconnections; Integrated circuit measurements; Integrated circuit packaging; Integrated circuit reliability; Power dissipation; Power system interconnection; Power system reliability; Temperature; Packaging; contact degradation; electromigration; flip-chip; high current testing; integrated circuit; interconnection technology; reliability; wire bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Workshop, 2007. IDT 2007. 2nd International

Conference_Location

Cairo

Print_ISBN

978-1-4244-1824-4

Electronic_ISBN

978-1-4244-1825-1

Type

conf

DOI

10.1109/IDT.2007.4437430

Filename

4437430