Generation of Power-Constrained Scan Tests and Its Difficulty

This paper proposes a test generation framework to generate stuck-at tests for a scan circuit under both peak shift and capture power limits. A concept of "complete fault efficiency under a power budget" is introduced, and it is pointed out that existing test-generation-based techniques for test power lack this completeness. Some analytical data obtained by using the proposed framework are presented to show the difficulty of generating test patterns that meet given limits for shift-in, shift-out and capture power, simultaneously. To relax the difficulty, this paper also describes a heuristic procedure using a cone analysis that definitely derives scan tests with low shift-in power and that reduces the search space during test generation. From the point of view discussed in this paper, further work should be undertaken in the future.