Title :
A trim memory employing both NPN and high-gain unijunction transistors
Author :
Panousis, Panagiotis
Author_Institution :
Bell Telephone Labs., Inc., NJ, USA
Abstract :
A three photo-mask flip-flop memory cell showing a cycle time of 500 ns will be described. Each cell contains four devices in an active area of 35 sq mil and uses 40 μW/bit holding power.
Keywords :
Conductivity; Coupling circuits; Diodes; Flip-flops; Laboratories; Resistors; Surface treatment; Switches; Telephony; Vehicles;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1971.1154942
