Low Power Small Area High Performance 2D-DCT architecture

This paper presents an efficient algorithm for implementing the Discrete Cosine Transform (DCT) with Distributed Arithmetic (DA). The proposed algorithm offers high speed and reduced area. The design is free of multipliers, ROM and ROM accumulators. Inner product computational module has been proved mathematically, to require only additions , The number of additions is decreased by dividing the adder array matrix before exploiting the redundancy in it .The proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, 15 additions, 4 subtractions are needed to complete the first phase of the calculations. Hardware implementation of the design is realized on xilinx fpga XC3S1000 .Savings exceed 95%.