DocumentCode
2851586
Title
Two-terminal transistor memory cell using breakdown
Author
Mar, Jeich
Author_Institution
Bell Telephone Labs., Inc., Murray Hill, NJ, USA
Volume
XIV
fYear
1971
fDate
17-19 Feb. 1971
Firstpage
10
Lastpage
11
Abstract
A transient charge storage memory cell utilizing a two-terminal transistor structure and junction breakdown will be described, illustrated by a simple fabrication scheme that avoids breakdown degradation. Experimental measurements on such cells will be offered.
Keywords
Degradation; Electric breakdown; Fabrication; High speed integrated circuits; Parasitic capacitance; Silicon; Telephony;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1971 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1971.1154948
Filename
1154948
Link To Document