SoC-Based Implementation of the Backpropagation Algorithm for MLP

The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be trained. It is shown that the speed of such a system is limited by the communication overhead between processing nodes, especially by the management of training vectors. Preliminary performance results on an Altera DE2-70 development board are given and optimal architecture parameters are selected.