A timing model for static CMOS gates

Author

Chen, H.-Y. ; Dutta, S.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

72

Lastpage

75

Abstract

A simple but accurate delay model is presented for both simple and complex static logic gates. Unlike the previous delay models which assume the worst-case scenario, the present model has the capability of handling the different input switching conditions. In the delay analysis of a circuit, failing to take into account the position of the transistor that is switching can result in a delay value which is off by a margin of 100% or more from the actual. This novel modeling technique has been implemented in LISP on a TI Explorer II workstation Lisp Machine as a part of the DROID design automation environment.<>

Keywords

CMOS integrated circuits; application specific integrated circuits; logic arrays; logic gates; DROID design automation environment; LISP; TI Explorer II workstation Lisp Machine; circuit; delay analysis; delay model; delay value; input switching conditions; static CMOS gates; static logic gates; switching transistor position; timing model; CMOS logic circuits; Circuit analysis; Delay; Design automation; Failure analysis; Logic gates; Semiconductor device modeling; Switching circuits; Timing; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76907

Filename

76907