DocumentCode
2851905
Title
MOSFET Scaling to Nanometer Regimes
Author
Hasaneen, El-Sayed A M ; Wahab, Mohamed A A ; Esmail, Osama N A
Author_Institution
El-Minia Univ., El-Minia
fYear
2007
fDate
16-18 Dec. 2007
Firstpage
261
Lastpage
264
Abstract
This paper presents the effect of the scaling-down of the MOSFET to nanometer regimes on the MOSFET performance. Cut-off frequency, transconductance, CMOS inverter delay and leakage tunneling current are computed. The cut-off frequency is investigated taking into consideration the gate drain and gate source overlap and the fringing capacitances. The effect of the oxide thickness scaling down on the gate tunneling current is computed. The results show that, at 5 nm channel length, the cut-off frequency can reach 150 GHz and the CMOS inverter delay can be less than 0.4 ps.
Keywords
CMOS integrated circuits; MOSFET; VLSI; nanoelectronics; CMOS inverter delay; MOSFET scaling; cut-off frequency; leakage tunneling current; nanometer regimes; threshold voltage; transconductance; Capacitance; Cutoff frequency; Delay effects; Energy consumption; Inverters; MOSFET circuits; Threshold voltage; Transconductance; Tunneling; Very large scale integration; CMOS inverter delay; MOSFET; Mobility; cut-off frequency; threshold voltage; tunneling current;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Test Workshop, 2007. IDT 2007. 2nd International
Conference_Location
Cairo
Print_ISBN
978-1-4244-1824-4
Electronic_ISBN
978-1-4244-1825-1
Type
conf
DOI
10.1109/IDT.2007.4437473
Filename
4437473
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