Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for low-variability nanoscale CMOS circuits

In this paper CMOS logic circuit performance of dopant-segregated Schottky barrier (DSSB) SOI and δ-doped partially insulated DSSB SOI (DSSB Pi-OX- δ) MOSFETs has been explored by extensive device/circuit simulations. It has been found that, the presence of partial buried oxide (BOX) and δ-doping in an n-channel and p-channel DSSB Pi-OX-δ MOSFETs not only improves the scalability but also reduces self-heating (SH) effect and the process induced threshold voltage variability of the devices. Further, although switching energy in DSSB SOI and DSSB Pi-OX-δ CMOS gates is almost equal, static power dissipation and the delay in DSSB Pi-OX-δ CMOS gates are reduced by ~75% and ~20% respectively over the DSSB SOI CMOS gates. Thus, employing partial BOX and δ-doping under the channel of DSSB SOI MOSFET not only eliminates the potential weaknesses of this device but also makes it suitable for nanoscale CMOS logic circuits.