Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch

SRAM-based memory arrays designed in deeply scaled technologies become increasingly susceptible to soft errors. A full account of SRAM cell stability requires dynamic noise margin models that take into account the temporal behavior of noise injection mechanism. One critical component of dynamic noise margin analysis is the determination of stability boundary, or the separatrix. Different from the unrealistic assumption made in prior work, we show that the separatrix is subject to significant perturbation due to device mismatch and hence must be carefully accounted for in noise margin analysis. More importantly, by applying a rigorous nonlinear system theory, we present an efficient separatrix tracing technique that can accurately determine the separatrix via fast transistor-level transient simulation. The presented technique is shown to be up to thousands times faster than a brute-force approach.