Cap-sharing technique to reduce on chip capacitance in semi-digital phase lock loops

With an ever increasing demand of low cost IC´s, of chips with smaller area and lower power consumption, a new semi-digital PLL architecture was proposed earlier [1]. This paper focuses on modifying this PLL architecture, to reduce the overall on chip capacitance further by discussing a technique of capacitance sharing among the N-semi digital storage cells. PLL using the proposed technique consumes less power and have smaller chip area than their digital counter part.