Event-EMU: an event driven timing simulator for MOS VLSI circuits

Author

Ackland, B.D. ; Clark, R.A.

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

80

Lastpage

83

Abstract

An event-driven approach to MOS timing simulation is presented, which has proved to be more efficient and reliable than time-step-based methods. The MOS network is statically partitioned into groups of strongly coupled nodes called regions. Regions are scheduled for evaluation using a priority event queue. Events are predictions of the time at which nodes within a region will change by more than a voltage threshold. Region evaluation is performed using a single modeling step followed by linear relaxation. The simulator has been used to verify the timing and functionality of a number of large (>500 K transistors) VLSI chips. Performance is 2-5 times faster than time-step-based methods and 200-300 times faster than circuit simulation.<>

Keywords

MOS integrated circuits; VLSI; circuit analysis computing; Event-EMU; MOS VLSI circuits; MOS network; MOS timing simulation; VLSI chips; evaluation scheduling; event driven timing simulator; functionality; linear relaxation; predictions; priority event queue; region evaluation; single modeling step; static partition; strongly coupled nodes; timing; transistors; verify; voltage threshold; Circuit simulation; Coupling circuits; Discrete event simulation; Logic circuits; MOS capacitors; Performance evaluation; Switches; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76909

Filename

76909