DocumentCode :
2852244
Title :
Library tuning for subthreshold operation
Author :
Bo Liu ; de Gyvez, Jose Pineda ; Ashouei, M.
Author_Institution :
Eindhoven Univ. of Technol., Eindhoven, Netherlands
fYear :
2012
fDate :
9-10 Oct. 2012
Firstpage :
1
Lastpage :
3
Abstract :
In this paper, the authors extend their work on the balancing-based subthreshold cell sizing methodology. The libraries were benchmarked against a library tuned for super-threshold operation. Two sets of standard cells have been properly sized for operation at 0.3V, and further characterized at different voltages. A super-threshold 90 nm low power library was chosen as a reference library to compare timing, power and voltage scaling ability. The resented libraries show a 31% timing improvement at 0.3 V without area penalty over the conventional library. The comparison of libraries at different voltages shows that with respect to the super-threshold library, the presented library with only transistor channel width tuning has on average 10% better timing from 0.3 V to 1.2 V, and that this library with both transistor channel width and length tuning show timing improvements of 31.4% and 6.9% when the supply voltage increases from 0.3 V to 0.6 V, respectively.
Keywords :
CMOS logic circuits; integrated circuit design; logic design; balancing based subthreshold cell sizing methodology; library tuning; low power library; size 90 nm; subthreshold operation; superthreshold operation; voltage 0.3 V to 1.2 V; Delay; Libraries; Loading; Standards; Transistors; Tuning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Subthreshold Microelectronics Conference (SubVT), 2012 IEEE
Conference_Location :
Waltham, MA
Print_ISBN :
978-1-4673-1586-9
Type :
conf
DOI :
10.1109/SubVT.2012.6404313
Filename :
6404313
Link To Document :
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