Ultra low-power filter bank for hearing aid speech processor

Author

Kwen-Siong Chong ; Barangi, M. ; Jaeyoung Kim ; Chang, Joseph S. ; Mazumder, Prasenjit

Author_Institution

Electr. & Electron. Eng. Dept., Nanyang Technol. Univ., Singapore, Singapore

fYear

2012

fDate

9-10 Oct. 2012

Firstpage

1

Lastpage

3

Abstract

An ultra-low power sub-threshold Finite Impulse Response (FIR) filter bank for hearing aid applications is demonstrated in 65nm CMOS technology. The system has a 2kb Static Random Access Memory (SRAM) interface optimized for sub-threshold operation. The system operates at 0.3V sub-threshold regime and consumes 10.4 μW at 0.96MHz clock frequency which corresponds to merely 0.6nJ per FIR operation.

Keywords

CMOS integrated circuits; FIR filters; SRAM chips; channel bank filters; hearing aids; low-power electronics; CMOS technology; FIR; SRAM; finite impulse response filter bank; frequency 0.96 MHz; hearing aid speech processor; power 10.4 muW; size 65 nm; static random access memory; ultra low-power filter bank; voltage 0.3 V; Channel bank filters; Clocks; Computer architecture; Filter banks; Finite impulse response filter; Microprocessors; Random access memory; FIR filter; SRAM; channel bank; dynamic power; leakage power; sub-threshold;

fLanguage

English

Publisher

ieee

Conference_Titel

Subthreshold Microelectronics Conference (SubVT), 2012 IEEE

Conference_Location

Waltham, MA

Print_ISBN

978-1-4673-1586-9

Type

conf

DOI

10.1109/SubVT.2012.6404314

Filename

6404314