DocumentCode
2852546
Title
Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip
Author
Molyneaux, Robert ; Ziaja, Tom ; Kim, Hong ; Aryani, Shahryar ; Hwang, Sungbae ; Hsieh, Alex
Author_Institution
SUN Microsystems, Austin, TX
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
8
Abstract
The Niagara2 System-on-Chip is SUN Microsystem´s latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO. It also showcases some excellent DFT results for this challenging system-on-chip design project.
Keywords
design for testability; logic design; logic testing; multiprocessing systems; system-on-chip; DFT results; Eco-sensitive CoolThreads line; Niagara2 CMP-CMT SPARC chip; SUN microsystem; bitmapping architecture; design for testability; hybrid flop design; multithreaded servers; system-on-chip; Clocks; Design for testability; Manufacturing; Network-on-a-chip; Random access memory; Registers; Scattering; Sun; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2007.4437561
Filename
4437561
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