A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes

Author

Sunter, Stephen ; Roy, Anirban

Author_Institution

Roy LogicVision (Canada) Inc., Ottawa, ON

fYear

2007

fDate

21-26 Oct. 2007

Firstpage

1

Lastpage

8

Abstract

A built-off self-test (BOST) approach is described in which a self-testing FPGA on a device-under-test (DUT) interface board can test serializers or deserializers at serial rates up to 6.4 Gbps, and some SerDes at much higher rates. With a few on-chip undersampling latches, the same BOST can also test embedded PLLs, DLLs, clocks, and logic delays. For SerDes functions, the structurally tested parameters include jitter and its constituent components, jitter tolerance, and waveshape. For other embedded functions, the tested parameters include jitter, duty cycle, frequency, phase error, and delay. The hardware results show that picosecond resolution has been achieved, with minimal or no changes to the DUT.

Keywords

built-in self test; field programmable gate arrays; phase locked loops; DLL; SerDes; built-off self-test; device-under-test interface board; duty cycle; high-frequency PLL; jitter tolerance; self-testing BOST; self-testing FPGA; waveshape; Automatic testing; Built-in self-test; Clocks; Delay; Field programmable gate arrays; Frequency; Hardware; Jitter; Logic devices; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2007. ITC 2007. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

978-1-4244-1127-6

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2007.4437571

Filename

4437571