Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs

As feature sizes continue to shrink for newer process technologies, signal integrity (SI) is emerging as a major concern for core-based system-on-a-chip (SoC) integrated circuits. To effectively test SI faults on core-external interconnects, core test wrappers need to be able to generate appropriate transitions at a wrapper output cell (WOC) on the driving side and detect the signal integrity loss at a wrapper input cell on the receiving side. In current wrapper designs, the WOCs for a victim interconnect and its aggressors make transitions at the same time with a common test clock signal in test mode, which is different from the functional mode. This is not adequate for SI test because the time elapsed between the transition of the victim and the transitions of its aggressors significantly affects the behavior of Si-related errors. To address this problem, we propose new IEEE Std. 1500-compliant wrapper designs that are able to apply SI test at functional mode or make transitions with various pre-defined skews between a victim line and its aggressors. We also introduce a novel overshoot detector inside the proposed wrapper. Experimental results show that the proposed wrapper designs are more effective for detecting Si-related errors when compared to existing techniques, with a moderate amount ofDFT overhead.