DocumentCode
2852781
Title
Experimental study of tri-gate SOI-FinFET flash memory
Author
Liu, Y.X. ; Kamei, Toshihiro ; Matsukawa, T. ; Endo, Kazuhiro ; O´uchi, S. ; Tsukada, J. ; Yamauchi, Hiroyuki ; Ishikawa, Yozo ; Hayashida, T. ; Sakamoto, Kazumitsu ; Ogura, Akira ; Masahara, M.
Author_Institution
Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan
fYear
2012
fDate
1-4 Oct. 2012
Firstpage
1
Lastpage
2
Abstract
It was experimentally confirmed that smaller Vt variations, better SCE immunity and a large memory window are obtained in the TG type SOI-FinFET flash memories than the DG type ones. The highly suppressed over erase was confirmed in the split-gate FinFET flash memories. Introducing a thin thermal oxide layer on the FG is useful to improve the IPD layer quality.
Keywords
MOSFET; flash memories; silicon-on-insulator; IPD layer quality; SCE immunity and; TG type SOI-FinFET flash memory; large memory window; short-channel effect immunity; split-gate FinFET flash memory; thin thermal oxide layer; trigate SOI-FinFET flash memory; Fabrication; FinFETs; Logic gates; Materials; Split gate flash memory cells;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference (SOI), 2012 IEEE International
Conference_Location
NAPA, CA
ISSN
1078-621X
Print_ISBN
978-1-4673-2690-2
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2012.6404366
Filename
6404366
Link To Document