Title :
A complete test set to diagnose scan chain failures
Author :
Guo, Ruifeng ; Huang, Yu ; Cheng, Wu-Tung
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR
Abstract :
In this paper, we present a test generation algorithm to improve scan chain failure diagnosis resolution. The proposed test generation algorithm creates a complete test set that guarantees each defective scan cell has unique failing behavior. This algorithm handles stuck-at fault and timing fault models. Problems and solutions that may happen in practical usage are discussed. We further extend the test generation algorithm to handle multiple failing scan chains and designs with embedded scan compression logic. Experimental results show the effectiveness of the proposed diagnostic test generation algorithm.
Keywords :
VLSI; automatic test pattern generation; design for testability; failure analysis; integrated circuit testing; DFT technique; defective scan cell; embedded scan compression logic; large VLSI circuits; scan chain failure diagnosis resolution; test generation algorithm; timing fault models; Circuit faults; Circuit testing; Fault diagnosis; Graphics; Logic testing; Production; Signal processing; Software testing; Test pattern generators; Timing;
Conference_Titel :
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1127-6
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2007.4437579