DocumentCode
2852864
Title
Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications
Author
Moreira, Jose ; Barnes, Heidi ; Hoersch, Guenter
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
10
Abstract
Relays are some of the most frequently used components on test fixtures for automated test applications. With data-rates of current I/O interfaces already reaching 5 Gbps and beyond in desktop applications and expected to continue to increase, test engineers must make the decision to continue using relays on the high-speed signal lines, or remove the relays from the test fixture signal paths and sacrifice the flexibility they provide. This paper presents some results and guidelines on using relays in test fixtures for 10 Gbps applications. A commercially available relay was selected and integrated into a typical ATE test fixture design. Special consideration was given to the footprint optimization through 3D-EM simulation and the use of passive equalization to compensate for some of the relay losses. The paper concludes with measurements of an experimental test fixture using an ATE system running 10 Gbps.
Keywords
automatic test equipment; automatic test pattern generation; semiconductor relays; 3D-EM simulation; ATE test fixture design; I/O interfaces; automated test applications; bit rate 5 Gbit/s to 10 Gbit/s; footprint optimization; high-speed signal lines; multigigabit ATE I/O characterization applications; passive equalization; relay losses; test fixture relays; test fixture signal paths; Automatic testing; Circuit testing; Costs; Digital relays; Electronic equipment testing; Fixtures; Instruments; Production; Switches; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2007.4437582
Filename
4437582
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