Title :
Testing of Vega2, a chip multi-processor with spare processors.
Author :
Makar, Samy ; Altinis, Tony ; Patkar, Niteen ; Wu, Janet
Author_Institution :
Azul Syst., Mountain View, CA
Abstract :
Vega2 is a CMP (chip multi-processor) with 48 processor cores, and several spare cores to improve yield. The chip also contains about 1000 memory macros both inside and outside the processor cores. The larger memories have column redundancy as well. The main DFT challenge for Vega2 is to produce an architecture that makes it easy to identify defective processors, thoroughly test the memories and efficiently apply ATPG patterns.
Keywords :
automatic test pattern generation; electronic engineering computing; logic testing; microprocessor chips; multiprocessing systems; ATPG patterns; Vega2 testing; chip multiprocessor; column redundancy; defective processors; memory macros; spare processor cores; Automatic test pattern generation; Built-in self-test; Costs; EPROM; Home appliances; Java; Logic testing; Packaging; Sun; System testing;
Conference_Titel :
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1127-6
Electronic_ISBN :
1089-3539
DOI :
10.1109/TEST.2007.4437584
