DocumentCode
2852892
Title
The design-for-testability features of a general purpose microprocessor
Author
Wang, Da ; Fan, Xiaoxin ; Fu, Xiang ; Liu, Hui ; Wen, Ke ; Li, Rui ; Li, Huawei ; Hu, Yu ; Li, Xiaowei
Author_Institution
Key Lab. of Comput. Syst. & Archit., Chinese Acad. of Sci., Beijing
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
9
Abstract
This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals.
Keywords
design for testability; logic design; microprocessor chips; design-for-testability feature; general purpose microprocessor; high-volume manufacturing; microprocessor design; optimized DFT architecture; CMOS technology; Circuit faults; Circuit testing; Clocks; Design for testability; Logic testing; Manufacturing; Microprocessors; Phase locked loops; Power dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2007.4437585
Filename
4437585
Link To Document