An efficient SAT-based path delay fault ATPG with an unified sensitization model

Automatic test pattern generation (ATPG) for path delay faults is an essential tool for structurally testing performance problems of circuits. The complexity issues of an ATPG are often due to the large number of selected target paths and assorted ways to sensitize these paths. In this paper, we tried to address the later problem by applying a SAT solver. First, we introduce a SAT model (CNF formats) for all sensitization criteria: robust, non-robust and function-sensitizable. Then, to ease the problem of re-constructing the circuit for every criteria in the SAT solver, we proposed to unify all sensitization under the same model. We also found that we could further save efforts of re-building the SAT model for every paths by sharing constraints. Applying the above techniques, we could achieve 10-1000 times of speedup for most benchmark circuits.