• DocumentCode
    2853116
  • Title

    Innovative capacitorless SOI DRAMs

  • Author

    Cristoloveanu, S. ; Bawedin, M. ; Wan, Jianwei ; Chang, Silvia ; Navarro, C. ; Zaslavsky, A. ; Le Royer, Cyrille ; Andrieu, F. ; Rodriguez, N. ; Gamiz, Francisco

  • Author_Institution
    IMEP-LAHC, Grenoble INP Minatec, Grenoble, France
  • fYear
    2012
  • fDate
    1-4 Oct. 2012
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that are usually regarded as parasitic phenomena.
  • Keywords
    MOSFET; SRAM chips; silicon-on-insulator; DRAM storage capacitor; MOS transistor scaling; coupling effects; floating body SOI MOSFET; floating-body 1T-DRAM; innovative capacitorless SOI DRAM; parasitic phenomena; Charge carrier processes; Couplings; Electric potential; Logic gates; Nonvolatile memory; Programming; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2012 IEEE International
  • Conference_Location
    NAPA, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4673-2690-2
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2012.6404391
  • Filename
    6404391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2853116