A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures

Test of phase-locked loops (PLLs) has been hampered by the complex mixed-signal nature of the system operation. While several built-in self-test (BIST) schemes have been proposed to reduce the cost of PLL test, a systematic BIST development methodology, specially targeting at the growing parametric failures in nanometer VLSI technologies, is yet to be developed. In this paper, we first present a detailed bottom- up parametric PLL macromodeling approach that is developed to realistically map the device-level process variations to the variations in system-level performances. Our parametric modeling techniques allow us to examine the correlations between the system performances and specific BIST measurements feasibly through behavioral-levels simulations. By exploiting our modeling infrastructure, an efficient methodology is then developed to facilitate evaluation and optimization of PLL BIST schemes. The proposed methodology is enabled by novel circuit-level macromodeling and powerful statistical dimension reduction techniques, the latter of which are employed to cope with the challenges imposed by the large number of process variations that must be considered. The application of our BIST development methodology is demonstrated by generating optimized BIST schemes that produce low mis-prediction levels for detection of parametric failures of charge-pump PLLs.