The new ATE: Protocol aware

Deep submicron shrinking IC geometries have enabled massive integration on an unprecedented level. Silicon companies with substantial IP libraries are able to manufacture a device that is a true "system " with diverse IP blocks in a single process on a single die. It is an ever increasing difficulty to adequately and cost effectively test a device at a "system level", let alone implement DFT for a "system " vs. a multitude of stand-alone IP blocks, each with their own test strategy. In the past 20 years, since the first mixed-signal or SOC ATE test systems appeared, there has not been any significant evolution in ATE architecture allowing for true system level test. This paper is a calling to automated test equipment suppliers (and silicon providers to help the call) to make a broad paradigm shift in ATE architecture that will enable true system level testing as part of the production test flow and methodology. ATE would be transformed from a simulation based environment to also include a real time protocol aware environment. Protocol aware ATE is possible, and it is drastically needed to achieve lowest possible defect rate, lowest cost, and fastest time to market for highly integrated semiconductors.