DocumentCode
2853343
Title
Synthesis of address generators
Author
Grant, D. ; Denyer, P.B. ; Finlay, I.
Author_Institution
Dept. of Electr. Eng., Edinburgh Univ., UK
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
116
Lastpage
119
Abstract
An approach is described for addressing generation hardware synthesis. The authors present algorithms and tools that describe the hardware between a binary counter and the address port of a block of memory, which is accessed in some repetitive pattern. These tools match results produced manually for examples taken from a VLSI image processing application.<>
Keywords
VLSI; computerised picture processing; logic CAD; storage allocation; VLSI image processing; address generators; address port; addressing generation hardware synthesis; binary counter; logic CAD; Counting circuits; Hardware; Image processing; Information retrieval; Power generation; Random access memory; Read-write memory; Signal processing; Signal processing algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76917
Filename
76917
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