Title :
Hierarchical test generation and diagnostics of differential cascode voltage switch circuits
Author :
Wu, D.M. ; Swanson, R.M. ; Davis, J.W.
Author_Institution :
IBM, Austin, TX, USA
Abstract :
Hierarchical methodologies for design-for-testability, test generation, and fault modeling of digital (DCVS) circuits are described. In addition to the 2× density and speed advantages over the conventional CMOS circuits, DCVS technology also has the following improved features: (1) DCVS can handle the test generation for an unlimited size chip. The testing problem is reduced to that of a logic group, and CPU time increases linearly as the number of logic groups increases. Fewer test patterns are required than for a CMOS chip of the same function. (2) Using different levels of diagnostics, DCVS can perform an exact diagnostic to a logic group, a logic tree, or a logic gate level. (3) A self-testable logic design can be easily implemented in DCVS by connecting outputs of each logic group with an XOR tree
Keywords :
built-in self test; design for testability; integrated logic circuits; logic testing; DCVS technology; XOR tree; design-for-testability; differential cascode voltage switch circuits; exact diagnostic; fault modeling; hierarchical test generation; logic gate level; logic group; logic tree; self-testable logic design; test generation; Automatic testing; CMOS logic circuits; CMOS technology; Central Processing Unit; Circuit faults; Circuit testing; Design methodology; Logic design; Logic testing; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.229929
